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Clockless circuit design in FDSOI
Marc Renaudin,CTO,Tiempo,France
Biography :
Marc Renaudin received the Engineering and PhD degrees in microelectronics and signal processing from the “Institut National Polytechnique” de Grenoble, France, respectively in 1987 and 1990. >From 1990 to 1998, he served as an assistant professor at Telecom Bretagne, a Graduate School of Telecommunications Engineering where he was in charge of the Grenoble entity. In 1998, he joined Grenoble-INP as a Professor and he founded the Concurrent Integrated Systems Research Group at Tima-Labs where he carried out research works on asynchronous circuit design, low-power and hardware security. In 2007, Professor Marc Renaudin co-founded Tiempo, a startup company located in Montbonnot St-Martin, near Grenoble (France), and became its CTO. Tiempo offers unique chip solutions and EDA tools for advanced ICs, exploiting its innovative clockless delay-insensitive design technology. Tiempo develops and qualifies high-end, secured and certified products for banking payment, open loop transit fare, e-government documents and IoT applications.
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